Features
- Certified 512-4096 bits capable RSA Crypto Core
- The core performs a classical modular exponentiation ^ where x is the plain text input which will be ciphered, y is the key input and the
module m input - Support all key sizes (512, 1024, 2048, 4096) and includes a complete testbench
- Required 4 memory cores: One single-port RAM and three FIFOs
- Direct addressing of all Registers
- Can be customized
- Any other pre-designed functions can be integrated into the FPGA.
- FPGA density and I/O requirements can be defined according to customer specifications.
- Designers should be familiar with cryptographic standards, VHDL, synthesis tools, FPGA Place and Route data flow and VHDL simulation software.
- Experience with microprocessors is recommended.
- The macro can easily be integrated into hierarchical VHDL designs.
NES-IPCORE-RSA | Certified 512-4096 bits capable RSA Crypto Core |