The FC-A429 macro implements a ARINC 429 protocole with Transmit and Receive Controllers . The macro controls all ARINC 429 bus specific sequences, protocol and timing. The FC-A429 macro interface allows the parallel-bus microprocessor to communicate bidirectionally with the ARINC 429 bus. This macro can be customized according to specific needs (application specific requirements). Any other predesigned functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specifications. Designers should be familiar with ARINC 429 standard,VHDL, synthesis tools, FPGA Place and Route data flow and VHDL simulation software. Experience with microprocessor is recommended. The macro can easily be integrated into hierarchical VHDL designs.
Features
- Independent Receivers (Rx) with FIFO
- Independent Transmitter (Tx) with FIFO
- Decoding signals interface type
- 16-Bit Data-bus
- Direct addressing of all Registers
- Support all ARINC 429 Data Rate Transfer
- Multi Label Capability
- Parity Control : Odd, Even, No Parity, Interrupt Capability
- Independent Interrupt Request Line for Rx and Tx Functions
- FPGA speed grade operating frequency dependant : system clock up to 70 MHz
- Can be customized
FC-A429 IP FPGA core for FMC-A429
