SE300 RF MIMO Solution
- Main Unit – PolarFire SOC FPGA from Microchip (MPFS460T-FCG1152);
- Slave units – PolarFire FPGA MPF500T-FCG1152;
- Flexible clock tree with JESD204B capability, based on HMC7044;
DSP8080-AIMM
- MIMO RF Tranceiver
- Dual 12-bit ADCs and dual 12-bit DACs
- Virtex-5 FXT FPGA (XC5VFX70T or XC5VFX100T)
- DDR2 SDRAM (1GByte per bank)
Dual RF MIMO
Based on Xilinx Zynq UltraScale+ family. Depending on the choice of Zynq device (XCZU7EV / XCZU7EG/ XCZU11EG / XCZU7CG in C1156 package) it can be used for video decoding/encoding, digital communication or image processing and AR/VR applications.
DSP8o2.11S
- IEEE802.11 a/b/g/- SISO and MIMO Development Platform
- Xilinx and Altera FPGAs (in Verilog/VHDL)
- FPGA control through 32 x 32 bit registers